Accurate measurement of current in a half-bridge phase of a buck mode DC-DC voltage converter, a reduced complexity diagram of which is shown in FIG. 1, has become a fundamental design issue in many CPU core power applications. Current measurement information is applied to three basic application objectives. The first, and usually the least demanding, is to identify an overcurrent condition. The second involves current balancing, either between different phases of a multiphase system, or between parallel configured DC-DC control systems that supply a common power node. The former situation is typically more demanding, and is directed at evenly distributing thermal effects and allowing lower current and power safety margins on the phase components (e.g., switching MOSFETs). The third objective, which is by far the most demanding need for accurate and precise current data, is the load-line specification for CPU systems. This effectively corresponds to a DC output impedance that would represent a much too high efficiency loss, if it were actually implemented with an output resistor. As a result the load-line is achieved by modulating the set-point voltage for the converter based on the current demand of the load. The basic problem being addressed is to monitor the current flowing into the load.
The half-bridge circuit of FIG. 1 is comprised of a high side NMOSFET 10 whose source-drain path is coupled in series with the source-drain path of a low side NMOSFET 20 between a power source 30 and ground (GND). Associated with the high side MOSFET 10 is a parasitic on-resistance RDSON10, while low side MOSFET 20 has a parasitic on-resistance RDSON20. An output inductor 40, which is coupled between a common phase node 15 and an output node 25, to which capacitor 35 and load 37 are coupled, has an effective series resistance ESR that is represented by parasitic resistor 50.
Although use may be made of only the above-referenced parasitic resistances of the half-bridge obtaining indirect measurement of the inductor current, each element has practical problems associated with it. For one thing, all three resistive components have manufacturing tolerances that must either satisfy system accuracy requirements or require calibration. Also, all three resistive elements have temperature dependencies which must be compensated if an accurate current measurement is to be inferred from the respective stages. Moreover, in all cases, if the converter is efficient, the voltages across these components are small so that noise is a concern.
For either of the two RDSONS the voltage measurement must be conducted during the time that the respective MOSFET is in the ON state (conducting). This requirement entails the difficulty of avoiding switching transients in the RDSON waveform. The high side (HS) RDSON10 measurement typically must be conducted during a very narrow time window due to voltage step down, and additionally the phase voltage at 15 must be referenced to the input power voltage. The low side (LS) RDSON20 measurement has a longer measurement interval available, but requires the measurement of a ground-referenced voltage that goes below ground. For the ESR, the DC component of a triangular waveform voltage is desired, so that filtering is implicit.
Of course, an auxiliary ‘measurement’ resistor could be inserted into any of the branches of the half-bridge to facilitate current measurement. However, doing so would introduce additional power dissipation losses and extra components in the design. As a consequence, measurement resistors are typically avoided if possible.
FIG. 2 diagrammatically illustrates a modification of the half-bridge of FIG. 1 to include a (relatively small area) pilot or current mirror NMOSFET 12 associated with the high side NMOSFET 10. The pilot device 12 has its gate and drain electrodes coupled in common with the respective gate and drain electrodes of the high side NMOSFET 10, while the source of the pilot device 12 is coupled to current monitoring circuitry 70. A determination of the current flow through the high side MOSFET 10 is based upon the current flowing through the pilot device 12 and the geometric ratio of the size of the pilot device 12 to that of the high side MOSFET 10. Although not explicitly shown it is understood that the current monitoring circuitry 70 must match the voltages on the source terminals of NMOSFETs 10 and 12. Because the pilot device 12 and the high side MOSFET 10 are located on the same substrate or die, thermal compensation is implicit. A principal disadvantage of this architecture is the necessity of using a specialized MOSFET (comprised of the combination of the high side MOSFET and its associated pilot device).
FIG. 3 diagrammatically illustrates a piloted approach that is similar to that of FIG. 2, except that the high side devices are PMOSFETs. This has the advantage of allowing relatively easy matching of the gate-to-source voltage in the high side PMOSFET 10 and the pilot device 12, while extracting the current measurement from the drain of the pilot device. Again the current monitoring circuitry 70 provides voltage matching for the drains of PMOSFETs 10 and 12. A disadvantage is the reduced performance of PMOS device compared with an NMOS device. Also a PMOS device is more costly and requires more gate drive than a comparable NMOS device.
In either of the piloted approaches of FIGS. 2 and 3, the easiest implementation is that where the power MOSFET, pilot MOSFET and current measurement circuitry are integrated together. However, this leads to a very expensive power transistor, when compared to using a discrete MOSFET. As a result, conventional piloted current measurement designs require a tradeoff between significant price (associated with cost of production) and performance.